Physical Design Engineer

We are looking for a Physical Design Engineer with 6+ years of ASIC physical design experience to drive block-level and full-chip implementation from RTL to GDSII for advanced technology nodes. Key Responsibilities Perform floorplanning, power planning, placement, CTS, routing, and timing closure. Resolve setup/hold violations, congestion, IR drop, and EM issues. Run DRC/LVS and support tapeout and signoff activities. Collaborate with RTL, DFT, STA, and verification teams. Required Skills Strong experience with Cadence Innovus or Synopsys ICC2. Proficiency in PrimeTime and Calibre. Expertise in timing closure, physical verification, and PPA optimization. Scripting skills in Tcl, Perl, or Python.

Experience in advanced nodes such as 5nm or less is preferred. #J-18808-Ljbffr