Sr Physical Design Engineer

Grow with us Ericsson Austin has an exciting opportunity for you in a fast-paced, highly collaborative technical environment. We are looking for a highly detailed person who loves problem solving and can tackle complex timing and power challenges in next‑gen SoCs, driving solutions that set new industry benchmarks. Ericsson Silicon develops tailor-made, high-performance solutions for present and future RAN needs.

Our Application Specific Integrated Circuits (ASICs) power cutting‑edge System on a Chip (SoC) – a game‑changer in telecommunications. With signal processors (DSPs) and accelerators, our technology enables high-performance, energy‑efficient, and lightweight network solutions. The role will work closely with engineering disciplines in Austin and Sweden to make sure that the final ASIC achieves the goals of the program.

What you will do: Be an empowered designer tasked with improving PPA of Ericsson ASICs Evaluate feasibility of architectural features through back end implementation Partner with front end design teams to address timing, power and congestion challenges Deliver a synthesized netlist to ASIC BE vendor, and collaborate with vendor to address physical design tradeoffs Work with DFT and architecture teams to develop timing constraints Provide technical leadership and direction for junior members of the team Participate in defining flows, methods and drive continuous improvement What you will bring: 10+ years of physical design experience and minimum of a BS in EE/CE Expert in one or many of these areas – methods to improve PPA, RTL checks and Synthesis, STA Constraints, DFT clocking architecture, physical design of high speed interface IPs Knowledge of System Verilog or VHDL Accomplished at problem resolution and execution per project plan/needs Prior experience in a Senior or Lead Engineer role, including direct responsibility for guiding and mentoring junior team members and setting technical direction Highly team oriented Highly desired experience: Good scripting skills in Tcl or Python Knowledge of low power implementation methodology through UPF Knowledge of RTL2GDS methodology in 5 nm or below technology nodes Compensation and Benefits Compensation for this position is dependent on various factors including location and candidate’s qualifications. The salary range for this position in Texas, USA is $162,000 to $243,000 . Your pay includes a short‑term variable compensation plan, allowing the opportunity for an annual bonus based on performance.

Health: Ericsson offers excellent health benefits, including three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Additional life, disability, and long‑term disability coverage is provided. Employees may also participate in the Stock Purchase Plan.

Financial security: The Ericsson US 401(k) Plan offers a 3% automatic company contribution and matching up to 100% of the employee’s contribution, with additional matching on further tiers as described. Time: New employees receive a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Paid maternity leave up to 16 weeks and parental or adoption leave up to 6 weeks at 100% pay.

Additional Benefits Ericsson offers additional company‑paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs. Primary country and city: USA | Austin, Texas Job details: Developer Recruiter name: Jim Everett Ericsson is an Equal Opportunity Employer. For additional information about accommodations due to a disability, contact Ericsson at hr.direct.americas@ericsson.com.

DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned. #J-18808-Ljbffr