Senior FPGA Design Engineer

Are you a Senior FPGA Design Engineer looking to join one of the top companies in the Aerospace and Defense industry? Are you looking to further your career and grow? Do you have experience in designing FPGA products with VHDL?

If you answered yes to those three questions, then apply today! Acara Solutions seeks highly qualified candidates to work ON-SITE with our client in Camden, NJ. Interested?

Responsibilities Lead FPGA Engineer - Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S/he will architect and implement FPGA designs, with hands‑on design/debug primarily for Ethernet, I2C, SPI, and AXI protocols. The client has state‑of‑the‑art EDA flows/methodologies, including Mentor EDA, Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus).

We are a learning organization and have the capability to target all FPGA vendors and have an ASIC front‑end capability, with mature design processes. Derive FPGA design specifications from system requirements. Develop a detailed FPGA architecture for implementation.

Implement design in RTL (VHDL) and perform module‑level simulations. Perform Synthesis, Place and Route (PAR), and Static Timing Analysis (STA). Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), Static Formal EDA.

Generate verification test plans and perform end‑to‑end simulations. Support Board, FPGA bring up. Validate design through HW/SW integration test with test equipment.

Support product collateral for NSA certification. Benefits Pay: $90.00 - $115.00 / hr. Hours: 9/80 hrs/Week.

Length: Temp-to-Perm (12 months). Job Requirements Required Skills / Qualifications: Associate Degree. Minimum 3 years of experience in designing FPGA products with VHDL.

Minimum 3 years of experience in Xilinx FPGAs and Vivado. Minimum 3 years of experience in a revision control system. Minimum 3 years of experience in Earned Value Management (EVM).

Preferred Skills / Qualifications: Bachelor's Degree (BS). Master's Degree (MS). PhD in Engineering or Engineering Technology or Chemistry or Physics or Mathematics or Data Science or Electrical or Electronics or Computer Engineering or Computer Science.

Good written, verbal, and presentation skills. Leadership capabilities. Experience with mapping algorithms to architecture.

Experience in C++ (OOP). Experience with any of the protocols: Ethernet, TCP/IP, PCIe, NVMe, USB. Experience with Xilinx SoC design with SDKs and PetaLinux OS.

Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult. Additional Information Upon offer of employment, the individual will be subject to a background check and a drug screen. In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire.

Active Secret Clearance. Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct) are an Equal Opportunity Employer. Race/Color/Gender/Religion/National Origin/Disability/Veteran.

Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status. #J-18808-Ljbffr