Senior Analog Design Engineer

Overview As the global leader in high-speed connectivity, Ciena is committed to a people‑first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well‑being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

How You Will Contribute The Wavelogic family of products are widely used in Ciena’s optical fiber transmission solutions and are one of the main contributors to Ciena’s success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track‑record of success over 30 years of evolution and revolution in the advancement of high‑speed circuits used in broadband fiber‑optic modems. This team pioneered the introduction of the world’s first high‑speed DAC and ADC analog macros that ushered in the era of coherent fiber‑optic product solutions.

We are looking for a hardworking senior analog design engineer who will lead the design of advanced high‑speed analog circuits in the latest deep‑submicron CMOS technologies. Responsibilities Perform feasibility work with various circuit topologies to recommend the best solution, weighing trade‑offs and discussing these with other team members including system groups to guide the formation of a circuit requirement specification. Carry out complete and detailed design of the analog blocks assigned, collaborating closely with the analog layout team and junior designers, and deliver full GDSII files to Ciena’s integration partner.

Report status updates regularly, participate in team meetings, and share experience with the rest of the group. Characterize analog circuits in Ciena’s state‑of‑the‑art lab from test‑chips through to full product implementation, working with members of the Analog Macro Integration team. Qualifications Electrical, computer engineering, computer science or other applicable scientific degree at the BEng/BSc, MEng/MSc, or Ph.D. level.

Minimum of 5 years industrial experience leading designs in advanced CMOS technology. Highly motivated self‑starter capable of working independently while being a great teammate. Ability to methodically address sophisticated technical problems.

Excellent organization, written and oral (English) interpersonal skills. Proficiency with Cadence, Mentor and Synopsys tools for analog design (Virtuoso, Calibre, STAR‑RC, MMSIM) at above intermediate level. History of successful analog circuit product deliveries.

Assets Experience with 2.5D or 3D E‑M tools such as HFSS or EMX. Experience with team‑leadership within an analog macro design group. Architect or system design experience for complex analog macro IP solutions using tools such as MATLAB and/or C++.

Experience with mixed‑signal design validation using state‑of‑the‑art probing and test equipment. Salary and Benefits The annual salary range for this position is $114,000 – $182,000 CAD. Pay ranges at Ciena accommodate variations in knowledge, skills, experience, market conditions, and locations.

Non‑Sales employees may be eligible for a discretionary incentive bonus; Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package including medical, dental, and vision plans, participation in a 401(K) (USA) and DCPP (Canada) with company matching, Employee Stock Purchase Program, Employee Assistance Program, company‑paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

Equal Opportunity Statement At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. #J-18808-Ljbffr