Hardware Engineer

PamirAI is a U.S.-based hardware startup building the Agent Computer — hardware that turns segmented time in your life into productivity. We're backed by top-tier U.S. VCs, with a founding team out of Microsoft and Qualcomm, shipping real products from 0→1 into production. This is a 3-month contract role based on-site in Redwood City, CA, with the option to convert to full-time based on performance. Full-time salary ranges from $150K to $200K depending on experience. During the contract, you'll focus primarily on design verification of our current platforms, plus small PCB prototype design as needed. After conversion to full-time, the role shifts toward PCB design ownership — schematics, layout, and bring-up on new boards and revisions. We're currently bringing up our device through EV2 → DVT → NPI. We have a comprehensive CTQ test plan spanning PMIC sequencing, power rails, USB-PD, wireless, audio, sensors, security, and reliability.

Success in this role means executing these tests end-to-end, documenting cleanly, and closing out findings with the design team — then graduating into a core PCB design seat on future products. Responsibilities Execute CTQ tests against EV2/DVT hardware: power sequencing, USB-PD negotiation, I²C/SPI bus integrity, PCIe/eMMC/SD storage, Wi‑Fi/BT/LTE RF, audio path, IMU, security elements, biometrics, RTC, thermals, and reliability soaks Set up and run benches with oscilloscopes, logic analyzers, power profilers, audio analyzers, thermal chambers, PD analyzers, and NFC fixtures Capture waveforms, log data, and file issues with proper root‑cause analysis — not just pass/fail Support small PCB prototype spins as needed during the contract Collaborate with the mechanical and firmware team in Shenzhen After conversion to full‑time — PCB Design Own schematic capture and PCB layout for new boards and revisions (4–10+ layers) Drive DFM/DFT reviews, BOM, assembly drawings, and manufacturing documentation Lead board bring‑up: power‑tree validation, clocking/reset, pin‑mux, high‑speed interface debug Work with firmware, industrial design, and supply chain through prototype → small batch → mass production Qualifications Must‑have (for the contract): 3+ years hands‑on hardware validation on embedded SoC platforms (If you think are a cracked engineer you can ignore this) Fluent with oscilloscopes ≥1 GHz bandwidth, logic analyzers, USB/PD analyzers, and spectrum analyzers Reads schematics at the discrete level — PMIC datasheets, load switches, level shifters Authorized to work in the U.S. and able to work on‑site in Redwood City, CA Nice‑to‑have USB‑C PD3.1, DisplayPort Alt Mode, and MIPI CSI debugging Wireless compliance (FCC / CE / SRRC) pre‑scan familiarity Python / Bash for test automation Spoken Mandarin for collaboration with our Shenzhen team For full‑time conversion Proven end‑to‑end PCB design experience, from schematic to layout to bring‑up, on 4–10+ layer boards Proficiency with Cadence Allegro (this is our design environment) High‑speed design experience with DDR/eMMC, USB 2/3, MIPI CSI/DSI, and PCIe constraint‑driven routing Exposure to SI/PI analysis, EMI/EMC pre‑scan and rework, and NPI / mass production introduction Passionate about consumer electronics What you get here Direct impact on 0→1 hardware shaping how humans and AI work together A seat at the table, not a seat in a row — your designs, your calls, your name on them Small team, fast iteration, competitive comp + equity on conversion Work alongside senior engineers from Microsoft, Qualcomm, and top U.S. VC‑backed startups Real products on real production lines — not demos, not decks #J-18808-Ljbffr